Specification And Design Methodology For Real-Time Embedded Systems 2001 Edition

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Springer Specification And Design Methodology For Real-Time Embedded Systems 2001 Edition by Randall S. Janka

Specification and design methodology has seen significant growth as a research area over the last decade tracking but lagging behind VLSI design technology in general and the CAD industry in particular. The commercial rush to market tries to leverage existing technology which fuels CAD design tool development. Paralleling this is very active basic and applied research to investigate and move forward rational and effective methodologies for accomplishing digital design especially in the field of hardware/software codesign. It is this close relationship between industry and academia that makes close cooperation between researchers and practitioners so important-and monographs like this that combine both abstract concept and pragmatic implementation deftly bridge this often gaping chasm. It was at the IEEE/ACM Eighth International Symposium on Hardware/Software Codesign where I met the author of this monograph Dr. Randall Janka who was presenting some of his recent dissertation research results on specification and design methodology or as he has so succinctly defined this sometimes ambiguous concept "the tools and rules." Where so many codesign researchers are trying to prove out different aspects of codesign and using toy applications to do so Dr. Janka had developed a complete specification and design methodology and prototyped the infrastructure-and proven its viability utility and effectiveness using a demanding real-world application of a real-time synthetic aperture radar imaging processor that was implemented with embedded parallel processors. Table of contents : List of Figures. List of Tables. List of Acronyms. Foreword. Preface. Acknowledgements. 1: Introduction. 1.1. The Basic Problem. 1.2. Solution to The Problem. 1.3. Contributions. 1.4. Organization. 1.5. Convergence of Research Threads. 2: Problem Background. 2.1. Background. 2.2. The Domain-specific Problem. 2.3. A Domain-specific Solution. 3: System Requirements & Intrinsic SDM Assessment. 3.1. System Requirements Specification Domains. 3.2. Domain-relevant Models of Computation. 3.3. Best MOCs for Domain-specific Specification Axes. 3.4. Implicit Framework MOCs. 3.5. Comparing The Monolithic Frameworks. 4: Quantified Extrinsic SDM Assessment. 4.1. A Unified Specification-modeling Methodology Evaluation Framework. 4.2. Quantification of SARKAR Basis. 4.3. Using Quantified Basis to Characterize Case SDM Frameworks. 4.4. Conclusion. 5: Extending Gajski's SER Methodology. 5.1. Background. 5.2. Parallels Between Gajski's SER & our ADOI. 5.3. Extending Gajski's SER to our ADOI. 6: the Magic Specification & Design Methodology. 6.1. Overview of the Magic Methodology. 6.2. Establishing Model Continuity. 6.3. 'Rules' Steps of the Magic SDM. 6.4. 'Tools' Frameworks Integrated Into the Magic SDM. 6.5. Model Continuity Via Middleware. 7: Case Study: Validating the Magic SDM Using a SAR Processor Application. 7.1. RASSP SAR Benchmark Overview. 7.2. Tabulate Requirements. 7.3. Capture Non-constraint Requirements in An Executable Model. 7.4. Build Executable Workbook with Requirements. 7.5. Gather Benchmarks for Tokens. 7.6. Explore Alternative Architectures & Technologies. 7.7. Make Design Decisions. 7.8. Create Implementation Specification. 7.9. Difficulties Encountered & Overcome. 7.10. Conclusion. 8: Magic Quantification & Summary. 8.1. Model Continuity in the Magic SDM. 8.2. SARKAR Quantification of Magic SDM. 8.3. Summary. 9: Conclusion: Directions for Further Research & Applying Magic to SOC Domain. 9.1. Applied & Basic Research. 9.2. Applying Magic Concepts to the SOC Domain. 9.3. Virtual Component Codesign (VCC). 9.4. Codesign vis a vis Coverification. 9.5. Concluding Comments. Appendix A: Details of VSIPL & MPI Middleware. A.1. VSIPL: Computation Middleware. A.2. MPI: Communications Middleware. Appendix B: Details of Case Study. B.1. Simulink Details. B.2. VSIPL Code Generation Subtleties. B.3. Earchitect Details. References. Index.