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Test Pattern Generation Using Boolean Proof Engines 2009 Edition at Meripustak

Test Pattern Generation Using Boolean Proof Engines 2009 Edition

Books from same Author: Rolf Drechsler Stephan Eggersglüß Goerschwin Fey Daniel Tille

Books from same Publisher: Springer

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    • General Information  
    Author(s)Rolf Drechsler Stephan Eggersglüß Goerschwin Fey Daniel Tille
    PublisherSpringer
    ISBN9789048123599
    Pages192
    BindingHardback
    LanguageEnglish
    Publish YearMay 2009

    Description

    Springer Test Pattern Generation Using Boolean Proof Engines 2009 Edition by Rolf Drechsler Stephan Eggersglüß Goerschwin Fey Daniel Tille

    In Test Pattern Generation using Boolean Proof Engines we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then the formulation as a SAT problem is considered. As the underlying engine modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation encoding of multiple-valued logic usage of various fault models and detailed experiments on multi-million gate designs. The book describes the state of the art in the field highlights research aspects and shows directions for future work. Table of contents : 1 Introduction. 2 Preliminaries. 2.1 Circuits. 2.2 Fault Models. 2.3 Simple ATPG Framework. 2.4 Classical ATPG Algorithms. 2.5 Benchmarking. 3 Boolean Satisfiability. 3.1 SAT Solver. 3.2 Advances in SAT.3.3 Circuit-to-CNF Conversion. 3.4 Circuit-oriented SAT. 4 SAT-based ATPG. 4.1 Basic Problem Transformation. 4.2 Structural Information. 4.3 Experimental Results. 4.4 Summary. 5 Learning Techniques. 5.1 Introductory Example. 5.2 Concepts for Reusing Learned Information. 5.3 Heuristics for ATPG. 5.4 Experimental Results. 5.5 Summary. 6 Multiple-valued Logic. 6.1 Four-Valued Logic. 6.2 Multi-input Gates. 6.3 Experimental Results. 6.4 Summary. 7 Improved Circuit-to-CNF Conversion. 7.1 Hybrid Logic. 7.2 Incremental Instance Generation. 7.3 Experimental Results. 7.4 Summary. 8 Branching Strategies. 8.1 Standard Heuristics of SAT Solvers. 8.2 Decision Strategies. 8.3 Experimental Results. 8.4 Summary. 9 Integration into Industrial Flow. 9.1 Industrial Environment. 9.2 Integration of SAT-based ATPG. 9.3 Test Pattern Compactness. 9.4 Experimental Results. 9.5 Summary. 10 Delay Faults. 10.1 Transition Delay. 10.2 Path Delay. 10.3 Encoding Efficiency for Path Delay Faults. 10.4 Incremental Approach. 10.5 Experimental Results. 10.6 Summary. 11 Summary and Outlook. Bibliography. Index.