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Formal Semantics And Proof Techniques For Optimizing Vhdl Models at Meripustak

Formal Semantics And Proof Techniques For Optimizing Vhdl Models

Books from same Author: Umamageswaran K.

Books from same Publisher: Springer

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    • General Information  
    Author(s)Umamageswaran K.
    PublisherSpringer
    Edition1999 Ed
    ISBN9780792383758
    Pages158
    BindingHardback
    LanguageEnglish
    Publish YearNovember 1998

    Description

    Springer Formal Semantics And Proof Techniques For Optimizing Vhdl Models by Umamageswaran K.

    Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL